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1/15 may 2002 m40z111 m40z111w 5v or 3v nvram supervisor for up to two lpsrams features summary n convert low power srams into nvrams n precision power monitoring and power switching circuitry n automatic write-protection when v cc is out-of-tolerance n choice of supply voltages and power-fail deselect voltages: C m40z111: v cc =4.5to5.5v ths = v ss ;4.5 v pfd 4.75v ths = v out ;4.2 v pfd 4.5v C m40z111w: v cc = 3.0 to 3.6v ths = v ss ;2.8 v pfd 3.0v v cc = 2.7 to 3.3v ths = v out ;2.5 v pfd 2.7v n less than 15ns chip enable access propagation delay (for 5.0v device) n packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) n soic package provides direct connection for a snaphat top which contains the battery figure 1. 28-pin soic package soh28 (mh) snaphat (sh) battery 28 1
m40z111, m40z111w 2/15 table of contents summarydescription...........................................................3 logicdiagram(figure2.).........................................................3 signalnames(table1.)..........................................................3 soic28connections(figure3.)....................................................3 hardwarehookup(figure4.) ......................................................4 maximumrating.................................................................4 absolutemaximumratings(table2.) ...............................................4 dc and ac parameters. . ........................................................5 dc and ac measurement conditions (table 3.) . . . .....................................5 ac testing load circuit (figure 5.) ..................................................5 capacitance (table 4.) . . . ........................................................5 dccharacteristics(table5.) ......................................................6 operation......................................................................7 dataretentionlifetimecalculation .................................................7 powerdowntiming(figure6.).....................................................8 poweruptiming(figure7.).......................................................8 powerdown/upaccharacteristics(table6.).........................................9 v cc noise and negative going transients . ...........................................9 supplyvoltageprotection(figure8.)................................................9 partnumbering ...............................................................10 batterytable(table8.)..........................................................10 package mechanical information . . . ..........................................11 revisionhistory...............................................................14
3/15 m40z111, m40z111w summary description the m40z111/w nvram supervisor is a self- contained device which converts a standard low- power sram into a non-volatile memory. a precision voltage reference and comparator monitors the v cc input for an out-of-tolerance con- dition. when an invalid v cc condition occurs, the condi- tioned chip enable (e con ) output is forced inactive to write-protect the stored data in the sram. during a power failure, the sram is switched from the v cc pin to the lithium cell within the snaphat ? to provide the energy required for data retention. on a subsequent power-up, the sram remains write protected until a valid power condition returns. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat housing contain- ing the battery. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mount- ing. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped sep- arately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery package (e.g., snaphat) part number is m4z28- br00sh or m4z32-br00sh (see table 8, page 10). figure 2. logic diagram table 1. signal names figure 3. soic28 connections ai02238b ths v cc m40z111 m40z111w e con v ss e v out ths threshold select input e chip enable input e con conditioned chip enable output v out supply voltage output v cc supply voltage v ss ground nc not connected internally ai02239b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 nc nc nc nc v cc nc v cc nc nc nc nc nc nc nc e nc nc nc nc nc ths nc v ss e con nc nc v out v cc m40z111 m40z111w
m40z111, m40z111w 4/15 figure 4. hardware hookup maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. ai02394 v cc e e2 e con v ss v out v cc cmos sram x8 or x16 3.0, 3.3, or 5v ths e 0.1 m f 0.1 m f m40z111/w thereshold 1n5817 or mbr5120t3 symbol parameter value unit t a ambient operating temperature grade 6 C40 to 85 c t stg storage temperature (v cc off) snaphat ? C40 to 85 c soic C55 to 125 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to v cc +0.3 v v cc supply voltage m40z111 C0.3 to 7.0 v m40z111w C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
5/15 m40z111, m40z111w dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions note: note that output hi-z is defined as the point where data is no longer driven. figure 5. ac testing load circuit note: 1. 50pf for m40z111w. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v (m40z111) or 3.3v (m40z111w); sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected parameter m40z111 m40z111w v cc supply voltage 4.5 to 5.5v 2.7 to 3.6v ambient operating temperature C40 to 85c C40 to 85c load capacitance (c l ) 100pf 50pf input rise and fall times 5ns 5ns input pulse voltages 0to3v 0to3v input and output timing ref. voltages 1.5v 1.5v ai02326 c l = 100pf (1) or 5pf c l includes jig capacitance 645 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 8 pf c out (3) output capacitance 10 pf
m40z111, m40z111w 6/15 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. outputs deselected. sym parameter test condition (1) m40z111 m40z111w unit min typ max min typ max i cc supply current outputs open 3 6 2 4 ma i ccdr data retention mode current 150 150 na i li input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i out1 v out current (active) v out >v cc C0.3 160 100 ma v out >v cc C0.2 100 65 ma i out2 v out current (battery back-up) v out >v bat C0.3 100 100 a v bat battery voltage 2.0 3.0 3.5 2.0 3.0 3.5 v v ih input high voltage 2.2 v cc +0.3 2.0 v cc +0.3 v v il input low voltage C0.3 0.8 C0.3 0.8 v v oh output high voltage i oh = C2.0ma 2.4 2.4 v v ohb v oh battery back-up i out2 = C1.0a 2.0 2.9 3.6 2.0 2.9 3.6 v v ol output low voltage i ol = 4.0ma 0.4 0.4 v ths threshold select voltage v ss v out v ss v out v v pfd power-fail deselect voltage (ths = v ss ) 4.50 4.60 4.75 2.80 2.90 3.00 v power-fail deselect voltage (ths = v out ) 4.20 4.35 4.50 2.50 2.60 2.70 v v so battery back-up switchover voltage 3.0 v pfd C 100mv v
7/15 m40z111, m40z111w operation the m40z111/w, as shown in figure 4, page 4, can control up to two standard low-power srams. these srams must be configured to have the chip enable input disable all other input signals. most slow, low-power srams are configured like this, however many fast srams are not. during normal operating conditions, the conditioned chip enable (e con ) output pin follows the chip enable (e ) input pin with timing shown in table 6, page 9. an internal switch connects v cc to v out .this switch has a voltage drop of less than 0.3v (i out1 ). when v cc degrades during a power failure, e con is forced inactive independent of e . in this situa- tion, the sram is unconditionally write protected as v cc falls below an out-of-tolerance threshold (v pfd ). the power fail detection value associated with v pfd is selected by the ths pin and is shown in table 5, page 6. note: the ths pin must be connected to either v ss or v out . if chip enable access is in progress during a power fail detection, that memory cycle continues to com- pletion before the memory is write protected. if the memory cycle is not terminated within time t wp , e con is unconditionally driven high, write protect- ing the sram. a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the sram's contents. at voltages below v pfd (min), the user can be as- sured the memory will be write protected provided the v cc fall time exceeds t f . as v cc continues to degrade, the internal switch disconnects v cc and connects the internal battery to v out . this occurs at the switchover voltage (v so ). below the v so , the battery provides a volt- age v ohb to the sram and can supply current i out2 (see table 5, page 6). when v cc rises above v so ,v out is switched back to the supply voltage. output e con is held inactive for t er (200ms maximum) after the power supply has reached v pfd , independent of the e input, to allow for processor stabilization (see figure 7, page 8). data retention lifetime calculation most low power srams on the market today can be used with the m40z111/w nvram supervi- sor. there are, however some criteria which should be used in making the final choice of which sram to use. the sram must be designed in a way where the chip enable input disables all other inputs to the sram. this allows inputs to the m40z111/w and srams to be don't care once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc =2.0v. the chip enable access time must be sufficient to meet the system needs with the chip enable prop- agation delays included. if the sram includes a second chip enable pin (e2), this pin should be tied to v out . if data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0v. manufacturers generally specify a typical condi- tion for room temperature along with a worst case condition (generally at elevated temperatures). the system level requirements will determine the choice of which value to use. the data retention current value of the srams can then be added to the i ccdr value of the m40z111/w to determine the total current requirements for data retention. the available battery capacity for the snaphat ? of your choice can then be divided by this current to determine the amount of data retention avail- able (see table 8, page 10). for more information on battery storage life refer to the application note an1012.
m40z111, m40z111w 8/15 figure 6. power down timing figure 7. power up timing ai02396 v cc e e con tf tfb v ohb v pfd (max) v pfd (min) v so twpt v pfd ai02397 v cc e e con tr ter trb v ohb v pfd (max) v pfd (min) v so v pfd tedl tedh
9/15 m40z111, m40z111w table 6. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200 s after v cc passes v pfd (min). 3. v pfd (min) to v ss fall time of less than tfb may cause corruption of ram data. 4. t er (min) = 20ms for industrial temperature range - grade 6 device. v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 8) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recom- mends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 8. supply voltage protection symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t edl chip enable propagation delay m40z111 15 ns m40z111w 20 ns t edh chip enable propagation delay m40z111 10 ns m40z111w 20 ns t er (4) chip enable recovery 40 200 ms t wpt write protect time m40z111 40 150 s m40z111w 40 250 s ai00622 v cc 0.1 m f device v cc v ss
m40z111, m40z111w 10/15 part numbering table 7. ordering information scheme note: 1. the soic package (soh28) requires the battery package (snaphat ? ) which is ordered separately under the part number m4zxx-br00shx in plastic tube or m4zxx-br00shxtr in tape & reel form. caution : do not place the snaphat battery package m4zxx-br00sh in conductive foam as this will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 8. battery table example: m40z 111w mh 6 tr device type m40z supply voltage and write protect voltage 111=v cc = 4.5 to 5.5v; v pfd = 4.3 to 4.5v ths = v ss =4.5 v pfd 4.75v ths = v out = 4.2 v pfd 4.5v 111w = v cc = 2.7 to 3.6v; v pfd = 2.6 to 2.7v ths=v ss = 2.8 v pfd 3.0v v cc = 2.7 to 3.3v ths=v out = 2.5 v pfd 2.7v package mh (1) = soh28 temperature range 6 = C40 to 85c shipping method for soic blank = tubes tr = tape & reel part number description package m4z28-br00sh snaphat housing for 48mah battery sh m4z32-br00sh snaphat housing for 120mah battery sh
11/15 m40z111, m40z111w package mechanical information figure 9. soh28 C 28-lead plastic small outline, 4-socket battery snaphat, package outline note: drawing is not to scale. table 9. soh28 C 28-lead plastic small outline, battery snaphat, package mechanical data symbol mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
m40z111, m40z111w 12/15 figure 10. 4-pin snaphat housing for 48mah battery, package outline note: drawing is not to scale. table 10. 4-pin snaphat housing for 48mah battery, package mechanical data symbol mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
13/15 m40z111, m40z111w figure 11. 4-pin snaphat housing for 120mah battery, package outline note: drawing is not to scale. table 11. 4-pin snaphat housing for 120mah battery, package mechanical data symbol mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
m40z111, m40z111w 14/15 revision history table 12. document revision history date revision details september 2000 first draft issue 09/14/01 reformatted, toc added, changed dc characteristics (table 5); changed battery, ind. temperature information (tables 2, 6, 7, 8, figures 10, 11); corrected soic label (figure 3); added e2 to hookup (figure 4) 05/13/02 modify reflow time and temperature footnote (table 2)
15/15 m40z111, m40z111w information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com
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